1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to capacitors within the Fully Depleted Silicon-on-Insulator manufacturing technology.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits can include passive devices, such as resistors, inductors and/or capacitors.
As integration density of semiconductor devices increases, the area occupied by individual devices continues to shrink. Notwithstanding this, a capacitor for storing data of, for instance, a dynamic random access memory (DRAM) is required to have a sufficient capacitance, irrespective of the decrease in the area occupied by the capacitor. In addition to so-called native capacitors, which make use of the native or “parasitic” inter-metal capacity between metal lines in integrated circuits, there are metal-insulator-metal (MIM) capacitors. Accordingly, a metal-insulator-metal (MIM) capacitor, in which a lower electrode and an upper electrode are formed of metal and separated by a layer of insulating material, is being used in many integrated circuit products. Metal-insulator-metal capacitors can be used in CMOS, BICMOS and bipolar integrated circuits. Typical applications of metal-insulator-metal capacitors include filter and analog capacitors, for example, in analog-to-digital converters or digital-to-analog converters, decoupling capacitors, radio frequency coupling and radio frequency bypass capacitors in radio frequency oscillators, resonator circuits, and matching networks.
Capacitors of the art suffer from the following problems. Vertical natural capacitors and finger metal-oxide-metal capacitors show insufficient capacitance due to low values of the dielectric constants of the used ultra-low-k dielectrics that, in principle, require large areas to provide significant capacitance anyway. The voltage of lateral capacitors, on the other hand, is limited, in principle, by the operation reliability of the employed ultra-low-k dielectrics. Moreover, conventional MIM capacitors in metallization/wire layers demand complex integration schemes.
A plurality of passive capacitors are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance at the location of a fast switching transistor, and thus reduce voltage variations which may otherwise unduly affect the logic state represented by the transistor. Since these capacitors are usually formed in and on active semiconductor regions, significant die area is consumed by the decoupling capacitors. Typically, these capacitors are formed in a planar configuration over active semiconductor regions, which act as a first capacitor electrode. The capacitor dielectric is formed during the process of manufacturing gate insulation layers of field effect transistors, wherein the gate material is usually patterned along with gate electrode structures so as to serve as the second capacitor electrode. Thus, in addition to the significant consumption of die area, increased leakage currents may be encountered in devices requiring highly capacitive decoupling elements, thereby significantly contributing to the total static leakage consumption and, therefore, to the total power consumption of the integrated circuit. For sophisticated applications, in terms of power consumption and/or heat management, the high amount of static power consumption may not be acceptable, and, therefore, usually a so-called dual gate oxide processing may be used to increase the thickness of the dielectric layer of the capacitors, thereby reducing the leakage current of these elements.
With reference to FIGS. 1a-1c, a typical prior art process flow for forming a semiconductor device comprising a highly capacitive decoupling capacitor having a moderate leakage current will now be described. FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 at a specific manufacturing stage. The semiconductor device 100 comprises a substrate 101, for example a silicon substrate, including a first semiconductor region 130 for receiving a transistor element and a second semiconductor region 120 for receiving a decoupling capacitor of high capacitance. Thus, the semiconductor region 120 may, contrary to the semiconductor region 130, occupy a significant fraction of a functional block of the device 100. The first and second semiconductor regions 130, 120 are enclosed by respective isolation structures 102. The first semiconductor region 130 and, partially, the corresponding isolation structure 102, are covered by a mask layer 103 that may be comprised of photoresist. The second semiconductor region 120 comprises a surface portion 104 having severe lattice damage caused by an ion implantation, as indicated by 105.
A typical process flow for forming the semiconductor device as depicted in FIG. 1a includes sophisticated photolithography and etch techniques for defining the isolation structures 102, followed by a further photolithography step to pattern the resist mask 103. Subsequently, the ion implantation 105 is carried out with any appropriate ions, such as silicon, argon, xenon and the like, wherein a dose and energy are selected to create severe lattice damage in the portion 104, thereby significantly changing the diffusion behavior of the portion 104 during an oxidation process that is to be carried out subsequently.
FIG. 1b schematically shows the semiconductor structure 100 in an advanced manufacturing stage. A first dielectric layer 131, substantially comprised of silicon dioxide and having a first thickness 132, is formed on the first semiconductor region 130. A second dielectric layer 121, having a second thickness 122 and comprised of the same material as the first dielectric layer 131, is formed on the second semiconductor region 120. The first and the second dielectric layers 131 and 121 are formed by conventional oxidation in a high temperature furnace process or by a rapid thermal oxidation process. Due to the severe lattice damage of the surface portion 104, the oxygen diffusion in this surface portion 104 is significantly enhanced compared to silicon portions having a substantially undisturbed crystallinity, such as in the surface region of the first semiconductor region 130. Consequently, oxide growth in and on the second semiconductor region 120 is increased compared to the growth rate of the first semiconductor region 130 so that the first thickness 132 differs from the second thickness 122 by approximately 0.2-1.0 nm for a thickness of the first dielectric layer 131 on the order of 1-5 nm.
FIG. 1c schematically shows the semiconductor device 100 in a further advanced manufacturing stage, wherein a decoupling capacitor 140 is formed in and on the second semiconductor region 120, and a field effect transistor 150 is formed in and on the first semiconductor region 130. The transistor element 150 comprises a gate electrode 133 including, for example, highly doped polysilicon and a metal suicide portion 135. Moreover, sidewall spacers 134 are formed adjacent to sidewalls of the gate electrode 133. Source and drain regions 136, each including a metal silicide portion 135, are formed in the first semiconductor region 130. The capacitor 140 comprises a conductive electrode 123 comprised of the same material as the gate electrode 133 and formed over the second dielectric layer 121. The electrode 123 represents a first electrode of the capacitor 140. The capacitor electrode 123 includes a metal silicide portion 125 and is enclosed by sidewall spacer elements 124.
A typical process flow for forming the transistor element 150 and the capacitor 140 may include the following steps. A polysilicon layer may be deposited over the device as shown in FIG. 1b and may be patterned by well-known photolithography and etching techniques to create the capacitor electrode 123 and die gate electrode 133 in a common process. Subsequently, the drain and source regions 136 are formed by ion implantation, wherein intermittently the sidewall spacers 134 and the sidewall spacers 124 are formed so that the sidewall spacers 134 may act as implantation masks to appropriately shape the dopant concentration of the drain and source regions 136. Thereafter, the metal silicide portions 125 and 135 may be formed by depositing a refractory metal and initiating a chemical reaction between the metal and the underlying polysilicon of the capacitor electrode 123, the gate electrode 133 and the silicon in the drain and source regions 136.
As is evident from FIG. 1c, the capacitor 140 having the second dielectric layer 121 with the increased thickness 122 will exhibit a reduced leakage current rate compared to the corresponding leakage rate caused by the relatively thin first dielectric layer 131 having the second thickness 132 that is optimized to provide the required dynamic performance of the transistor 150. Although a remarkably improved leakage rate of the capacitor 140 may be obtained with the above-described conventional approach, one decisive drawback is the significantly reduced capacitance per unit area of the capacitor 140 owing to the increased thickness of the second dielectric layer 121. Thus, for a given desired charge storage capacity as required for an enhanced decoupling effect, an even more enlarged area is necessary for the capacitor 140. A further disadvantage of the conventional prior art approach is the requirement of a high temperature oxidation process for forming the first and second dielectric layers 131 and 121 so that this process scheme may not be compatible with alternative solutions for forming extremely thin gate dielectrics, such as advanced deposition methods for forming ultra-thin gate insulation layers. Moreover, the process flow described above leads to a highly non-uniform pattern density, i.e., regions with increased dimensions representing, for instance, the capacitor 140, are located in the vicinity of tiny regions such as the transistor 150, which may compromise the patterning process for forming the highly critical gate electrodes, such as the gate electrode 133. In view of the above-described situation, there is a need for an improved technique that enables the formation of capacitors, while avoiding, or at least reducing the effects of, one or more of the problems identified above.
Accordingly, there is a need for enhanced capacitor structures and formation processes, for example, for use in semiconductor device fabrication, which integrate well with SOI manufacturing techniques, in particular, Fully Depleted SOI (FDSOI) manufacturing techniques. The present disclosure provides enhanced capacitor structures and manufacturing processes for the same wherein the above-mentioned issues can properly be addressed and the mentioned problems of the art can be overcome or at least alleviated.